Receivers utilized in communication systems (e.g., Ethernet physical layer (PHY)) may include Decision feedback equalizers (DFE). The receivers are configured to receive transmitted digital data that has been serialized and modulated onto a carrier signal and transmitted over a channel and to recover the digital data. The received signal may be degraded by non-ideal characteristics of the channel (e.g., finite bandwidth). As a result, a sample of the received signal corresponding to a digital data bit may include contributions from previously transmitted bits (i.e., inter-symbol interference). DFEs are configured to utilize one or more prior decisions to reduce the effects of inter-symbol interference to facilitate recovery of the transmitted digital data.
Increasing data rates to on the order of tens and/or hundreds of gigabits per second (Gbps) creates challenges for DFE circuitry. For example, DFE circuitry contains a feedback loop and the feedback timing may be limited by the TCO (timing from clock to output) of clocked comparator circuitry (i.e., decision element) included in the DFE circuitry. Thus, operation of the DFE circuitry may be constrained by characteristics of the clocked comparator circuitry. Increasing the speed and/or the accuracy of the clocked comparator circuitry may result in an increase in size and/or an increase in power consumption of the DFE and associated receiver.
DFE circuitry may include a plurality of taps. Each tap corresponds to a respective prior decision weighted by a respective weight. Respective outputs of each tap of a plurality of taps are typically combined with a representation of the received signal, e.g., input data, in a summation node. Each tap acts as a load on the summation node and thus, may limit the bandwidth of the feedback loop. As the number of taps increases, the resulting load increases and the associated bandwidth may decrease. Bandwidth limitations may then result in an increased delay between an input to the DFE circuitry and an output from the DFE circuitry. Such delay can detrimentally affect timing, particularly at relatively high frequencies and corresponding relatively high data rates. The bandwidth limitations may limit loop gain. The limited loop gain may then be compensated by an increase in a number of variable gain amplifier (VGA) stages preceding the DFE circuitry. Increasing the number of VGA stages may increase a size and/or power consumption of the receiver circuitry.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.